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89C535/89C536/89C538 CMOS single-chip 8-bit microcontrollers with FLASH program memory
Preliminary specification IC20 Data Handbook 1997 June 05
Philips Semiconductors
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
DESCRIPTION
The 89C535/89C536/89C538 are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. The devices also have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, UART and on-chip oscillator and timing circuits. For systems that require extra data memory capability up to 64k bytes, each can be expanded using standard TTL-compatible memories and logic. The 89C535/89C536/89C538 contain a non-volatile FLASH EPROM program memory (8K bytes in 89C535, 16k bytes in the 89C536, and 64k bytes in the 89C538). The devices have 512 bytes of RAM data memory.
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2 T2 T2EX RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 PORT 2
PORT 3
FEATURES
ADDRESS BUS
* 80C51 Central Processing Unit * 8k x 8 (89C535) 16k x 8 (89C536) or 64k x 8 (89C538), FLASH
EPROM Program Memory
SU00830
* 512 x 8 RAM, externally expandable to 64k x 8 Data Memory * Three 16-bit counter/timers * Up to 3 external interrupt request inputs * 6 interrupt sources with 2 priority levels * Four 8-bit I/O ports * Full-duplex UART * Power control modes
- Idle mode - Power down mode, with wakeup from power down using external interrupt
* 44-pin PLCC and QFP packages
ORDERING INFORMATION
PART NUMBER P89C535NBA A P89C536NBA A P89C536NBB B P89C538NBA A P89C538NBB B MEMORY SIZE 8k bytes 16k bytes 16k bytes 64k bytes 64k bytes TEMPERATURE RANGE (C) AND PACKAGE 0 to +70, 44-pin Plastic Leaded Chip Carrier 0 to +70, 44-pin Plastic Leaded Chip Carrier 0 to +70, 44-pin Plastic Quad Flat Package 0 to +70, 44-pin Plastic Leaded Chip Carrier 0 to +70, 44-pin Plastic Quad Flat Package FREQ. (MHz) 33 33 33 33 33 DRAWING NUMBER SOT187-2 SOT187-2 SOT307-2 SOT187-2 SOT307-2
1997 Jun 05
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROF/EPROM
8 B REGISTER STACK POINTER
ACC
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU
BUFFER
SFRs PSW TIMERS PC INCREMENTER 8 PROGRAM COUNTER PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER 16
DPTR'S MULTIPLE
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00854
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39 1 LCC PQFP 33
17
29
11
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function VSS P1.0/T2 P1.1/T2EX P1.2/ECI P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VCC P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 12 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS VCC P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC VSS P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
* NO INTERNAL CONNECTION
SU00852A
* NO INTERNAL CONNECTION
SU00853A
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC VSS VCC P0.0-0.7 LCC 1, 22 23, 44 43-36 QFP 16, 39 17, 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EEPROM programming. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions for Port 1 include: 2 3 P2.0-P2.7 24-31 40 41 18-25 I/O I I/O T2 (P1.0): Timer/Counter 2 external count input T2EX (P1.1): Timer/Counter 2 Reload/Capture Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Some Port 2 pins receive the high order address bits during EEPROM programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EEPROM programming. Program Store Enable: The read strobe to external program memory. When the processor is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory. If EA is held high, the device executes from internal program memory. This pin also receives the 12V programming supply voltage (VPP) during EPROM programming. EA is internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
P1.0-P1.7
2-9
40-44, 1-3
I/O
P3.0-P3.7
11, 13-19
5, 7-13
I/O
11 13 14 15 16 17 18 19 RST ALE/PROG 10 33
5 7 8 9 10 11 12 13 4 27
I O I I I I O O I O
PSEN
32
26
O
EA/VPP
35
29
I
XTAL1 XTAL2
21 20
15 14
I O
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Table 1. Special Function Registers
SYMBOL ACC* B* DPTR: DPH DPL DESCRIPTION Accumulator B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low DIRECT ADDRESS E0H F0H 83H 82H AF IE* Interrupt Enable A8H EA BF IP* Interrupt Priority B8H - 87 P0* Port 0 80H AD7 97 P1* Port 1 90H - A7 P2* Port 2 A0H AD15 B7 P3* PCON# Port 3 Power Control B0H 87H RD SMOD D7 PSW* RACAP2H# RACAP2L# SBUF Program Status Word Timer 2 Capture High Timer 2 Capture Low Serial Data Buffer D0H CBH CAH 99H 9F SCON* SP Serial Control Stack Pointer 98H 81H 8F TCON* Timer Control 88H TF1 CF T2CON* TH0 TH1 TH2# TL0 TL1 TL2# TMOD Timer 2 Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode C8H 8CH 8DH CDH 8AH 8BH CCH 89H TF2 8E TR1 CE EXF2 8D TF0 CD RCLK 8C TR0 CC TCLK 8B IE1 CB EXEN2 8A IT1 CA TR2 89 IE0 C9 C/T2 88 IT0 C8 CP/RL2 00H 00H 00H 00H 00H 00H 00H 00H 00H SM0 9E SM1 9D SM2 9C REN 9B TB8 9A RB8 99 TI 98 RI 00H 07H CY AE - BE - 86 AD6 96 - A6 AD14 B6 WR - D6 AC AD ET2 BD PT2 85 AD5 95 - A5 AD13 B5 T1 - D5 F0 AC ES BC PS 84 AD4 94 - A4 AD12 B4 T0 - D4 RS1 AB ET1 BB PT1 83 AD3 93 - A3 AD11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 82 AD2 92 - A2 AD10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 - A8 EX0 B8 PX0 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P 00H 00H 00H xxxxxxxxB FFH 0xxxx000B FFH FFH FFH x0000000B 00H BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H 00H 00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET.
Design Consideration LOW POWER MODES Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
* To eliminate the possibility of an unexpected write when Idle is
terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to memory.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC51FA/FB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and
Table 2. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
TIMER 2 OPERATION Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes:Capture, Auto-reload, and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3.
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.).
Auto-Reload Mode
In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (C/T2* in T2CON). Figure 3 shows the auto-reload mode of Timer 2. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
Capture Mode
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register/SFR table). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is
(MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 EXF2 RCLK TCLK EXEN2 TR2 C/T2
(LSB) CP/RL2
Name and Significance
RCLK TCLK EXEN2
TR2 C/T2
CP/RL2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. T2CON.1 Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
SU00866
Figure 1.
Timer/Counter 2 (T2CON) Control Register
Table 3. Timer 2 Operating Modes
RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
OSC
/ 12 C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) TF2
T2 Pin
Control
TR2 Transition Detector
Capture Timer 2 Interrupt RCAP2L RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2.
Timer 2 in Capture Mode
OSC
/ 12 C/T2 = 0 TL2 (8-BITS) C/T2 = 1 TH2 (8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TF2 TIMER 2 INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 3.
Timer 2 in Auto-Reload Mode
1997 Jun 05
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Timer 1 Overflow
NOTE: OSC. Freq. is divided by 2, not 12. /2 C/T2 = 0 TL2 (8-bits) C/T2 = 1 T2 Pin Control TH2 (8-bits) "1"
/2 "0" "1" SMOD "0" RCLK
OSC
/ 16 TR2 "1" Reload "0"
RX Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
/ 16
TX Clock
T2EX Pin
EXF2
Timer 2 Interrupt
Control EXEN2 Note availability of additional external interrupt.
SU00068
Figure 4.
Timer 2 in Baud Rate Generator Mode The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below: Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 RCAP2L FF D9 B2 64 C8 1E AF 8F 57 The timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [32 [65536 * (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 4, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.
Table 4.
Timer 2 Generated Commonly Used Baud Rates
Timer 2 Osc Freq 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H FF FF FF FF FE FB F2 FD F9
Ba d Rate Baud 375K 9.6K 2.8K 2.4K 1.2K 300 110 300 110
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Figure 4 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 1997 Jun 05 10
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 4 shows commonly used baud rates and how they can be obtained from Timer 2.
If Timer 2 is being clocked internally , the baud rate is: Baud Rate + f OSC [65536 * (RCAP2H, RCAP2L)]]
[32
Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L + 65536 * f OSC Baud Rate
32
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Table 5. Timer 2 as a Timer
T2CON MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H
Table 6. Timer 2 as a Counter
TMOD MODE 16-bit Auto-Reload INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH
NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Serial Interface
The 89C538/536 has a standard 80C51 serial port. This serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (throughTxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1, Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. SCON Address = 98H Bit Addressable SM0 Bit: Symbol SM0 SM1 7 SM1 6 SM2 5 REN 4
Mode 3: 11 bits are transmitted (through TxD) or received (through jRxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
Serial Port Control Register
The serial port control and status register is the Special FunctionRegister SCON, shown in Figure 5. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Additional details of serial port operation may be found in the 80C51 Family Hardware Description found in the Philips 80C51-Based 8-Bit Microcontroller Data Handbook, IC20.
Reset Value = 0000 0000B
TB8 3
RB8 2
Tl 1
Rl 0
Function Serial Port Mode Bit 0 Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
SU00867
REN TB8 RB8 Tl Rl
NOTE: **fOSC = oscillator frequency
Figure 5.
SCON: Serial Port Control Register
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Interrupt Priority Structure
The 89C535/536/538 has a 6-source two-level interrupt structure (see Table 7). There are 2 SFRs associated with the interrupts on the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.) The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS INTERRUPT PRIORITY LEVEL IP.x 0 1 Level 0 (lowest priority) Level 1 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
Table 7.
Interrupt Table
POLLING PRIORITY 1 2 3 4 5 6 REQUEST BITS IE0 TP0 IE1 TF1 R1, TI TF2, EXF2 HARDWARE CLEAR? N (L)1 Y N (L) Y (T) Y N N Y (T)2 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH X0 T0 X1 T1 SP T2
SOURCE
NOTES: 1. L = Level activated 2. T = Transition activated
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
7 IE (0A8H) EA
6 --
5 ET2
4 ES
3 ET1
2 EX1
1 ET0
0 EX0
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL EA -- ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. Not implemented. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit. Figure 6. 7 IP (0B8H) -- 6 -- 5 PT2 4 PS IE Registers 3 PT1 2 PX1 1 PT0 0 PX0
SU00571
Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL -- -- PT2 PS PT1 PX1 PT0 PX0 FUNCTION Not implemented, reserved for future use. Not implemented, reserved for future use. Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. Figure 7. IP Registers
SU00572
1997 Jun 05
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Expanded Data RAM Addressing
The 89C535/536/538 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes expanded RAM (ERAM). The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 256-bytes expanded RAM (ERAM, 00H - FFH) are indirectly accessed by move external instruction, MOVX. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFRs. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0,#data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The ERAM can be accessed by indirect addressing and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256-bytes of external data memory. The ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, MOVX @R0,#data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e., 0100H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 8. External data memory cannot be accessed using the MOVX with R0 or R1. This will always access the ERAM. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.
FF
FF
FF
FFFF
UPPER 128 BYTES INTERNAL RAM
SPECIAL FUNCTION REGISTER
EXTERNAL DATA MEMORY
ERAM 256 BYTES
80
80
LOWER 128 BYTES INTERNAL RAM 0100 0000
00
00
00
SU00868
Figure 8.
Internal and External Data Memory Address Space
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin RATING 0 to +70 -65 to +150 0 to +13.0 -0.5 to +6.5 15 UNIT C C V V mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C; 5V 10%; VSS = 0V SYMBOL VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 3 6 Output low voltage, port 0, ALE, PSEN 5, 6 Output high voltage, ports 1, 2, 3 2 Output high voltage (port 0 in external bus mode), ALE7, PSEN2 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 3 Input leakage current, port 0 Power supply current (see Figure 16): Active mode Idle mode Power-down mode or clock stopped (see Fi Figure 20 f conditions) for ( diti ) VCC = 4.5V IOL = 1.6mA1 VCC = 4.5V IOL = 3.2mA1 VCC = 4.5V IOH = -30A VCC = 4.5V IOH = -800A VIN = 0.4V VIN = 2.0V See note 3 0.45 < VIN < VCC - 0.3 See note 4 VCC = 5.5V FREQ = 24 MHz Tamb = 0C to 70C VCC - 0.7 VCC - 0.7 -1 -50 -650 10 60 25 100 PARAMETER TEST CONDITIONS 4.5V < VCC < 5.5V LIMITS MIN -0.5 0.2VCC+0.9 0.7VCC MAX 0.2VCC-0.1 VCC+0.5 VCC+0.5 0.4 0.4 UNIT V V V V V V V A A A mA mA A
RRST Internal reset pull-down resistor 40 225 k NOTES: 1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 2. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. See Figures 17 through 20 for ICC test conditions. Active mode: ICC(MAX) = 0.9 x FREQ. + 1.1mA Idle mode: ICC(MAX) = 0.18 x FREQ. +1.0mA; See Figure 16. 5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF).
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V1, 2, 3 VARIABLE CLOCK SYMBOL 1/tCLCL FIGURE 9 PARAMETER Oscillator frequency Speed versions : N (33MHz) ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-80 0 tCLCL-25 17 17 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 0 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 5 5 360 167 50 0 5 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 40 45 0 5 80 0 55 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 32 90 105 140 0 tCLCL-25 5tCLCL-80 10 82 82 60 tCLCL-25 3tCLCL-45 3tCLCL-60 0 5 70 10 MIN 3.5 MAX 33 MHz 3.5 tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 12 12 12 12 ns ns ns ns 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 10, 11 11 10, 11 10, 11 13 13 13 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 9 9 9 9 9 9 9 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 5 45 30 21 5 5 55 33 ns ns ns ns ns ns ns ns ns ns ns 33MHz CLOCK MIN MAX UNIT
External Clock
tXHDV 12 Clock rising edge to input data valid 10tCLCL-133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 9.
External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 10.
External Data Memory Read Cycle
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 11.
External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 12.
Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 13.
External Clock Drive
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00717
SU00718
Figure 14.
AC Testing Input/Output
Figure 15.
Float Waveform
90.00 80.00 70.00 60.00 ICC(mA) 50.00 40.00 30.00 20.00 MAX IDLE MODE 10.00 0.00 0 4 8 12 16 20 TYP IDLE MODE 24 28 32 36 TYP ACTIVE MODE MAX ACTIVE MODE
FREQ AT XTAL1 (MHz)
SU00886
Figure 16.
ICC vs. FREQ Valid only within frequency specifications of the device under test
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 17. ICC Test Condition, Active Mode All other pins are disconnected
Figure 18. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 19.
Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 20. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
FLASH EPROM PROGRAM MEMORY FEATURES
does not require the system to time out or verify the data programmed. The typical room temperature chip programming time of the 89C535/536/538 is less than 5 seconds.
* 8K (89C535), 16K (89C536), 64K (89C538) or
erasable internal program. memory is switched off (EA = 0)..
Automatic Chip Erase
electrically The device may be erased using the automatic Erase algorithm. The automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device.
* Up to 64 Kilobyte external program memory if the internal program * Programming and erasing voltage 12V "5% * Command register architecture
- Byte Programming (10 us typical) - Auto chip erase 5 seconds typical (including preprogramming time)
Automatic Programming Algorithm
The 89C535/536/538 automatic Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.
* Auto Erase and auto program
- DATA polling - Toggle bit
* 100 minimum erase/program cycles * Advanced CMOS FLASH EPROM memory technology
GENERAL DESCRIPTION
The 89C535/536/538 FLASH EPROM memory augments EPROM functionality with In-circuit electrical erasure and programming. The 89C535/536/538 uses a command register to manage this functionality. The FLASH EPROM reliably stores memory contents even after 100 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The 89C535/536/538 uses a 12.0V "5%VPP supply to perform the Auto Program/Erase algorithms.
AUTOMATIC ERASE ALGORITHM
The 89C535/536/538 Automatic Erase algorithm requires the user to only write an erase set-up command and erase command. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation. Commands are written to the command register. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the 89C535/536/538 is designed to support either WE or CE controlled writes. During a system write cycle, addresses are latched on the falling edge of WE or CE, whichever occurs last. Data is latched on the rising edge of WE or CE, whichever occurs first. To simplify the following discussion, the WE pin is used as the write cycle control pin through the rest of this text. All setup and hold times are with respect to the WE signal.
Automatic Programming
The 89C535/536/538 is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm
1997 Jun 05
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
+5V VDD A0-A7 P1 P0 EA ALE/WE CE P3.3 89C535/536/538 XTAL2 P3.5 4-6 MHz P2.0-P2.5 XTAL1 VSS A15 A8-A13 PSEN P2.7 PGM COMMAND/DATA VPP LOW PULSE 0 OE
1
RST
P3.4 P2.6, P3.7, P3.1, P3.0
A14 0000b
su00876
Figure 21.
Erase/Programming/Verification
Table 8. Pin Description
PIN NAME P1.0-P1.7 P2.0-P2.5, P3.4, P3.5 P0.0-P0.7 P3.3 P2.7 ALE/WE EA P2.6, P3.7, P3.1, P3.0 VCC GND A0-A7 A8-A13, A14-A15 Q0-Q7 CE OE WE VPP FTEST3-FTEST0 VCC GND SYMBOL FUNCTION Input Low Order Address Bits Input High Order Address Bits Data Input/Output Chip Enable Input Output Enable Input Write Enable Pin Program Supply Voltage Flash Test Mode Selection Power Supply Voltage (+5V) Ground Pin
Table 9. Command Definitions
FIRST BUS CYCLE COMMAND Setup auto erase/auto erase (chip) Setup auto program/program Reset Note: 2 2 2 BUS CYCLES OPERATION ADDRESS DATA Write Write Write X X X 30H 40H FFH SECOND BUS CYCLE OPERATION ADDRESS DATA Write Write Write X PA X 30H PD FFH
* PA = Address of memory location to be programmed * PD = Data to be programmed at location
Command Definitions
When low voltage is applied to the VPP pin, the contents of the command register default to 00H. Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Table 2 defines these 89C535/536/538 register commands. Table 3 defines the bus operations of 89C535/536/538.
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
Table 10.
OPERATION READ/WRITE Read(2) Standby(4) Write VPPH VPPH VPPH VIL VIH VIL VIL X VIH VIH X VIL DATA OUT(3) Tri-State Data In(5) VPP(1) CE OE WE D00-D07
NOTES: 1. VPPH is the programming voltage specified for the device. 2. Read operation withVPP = VPPH may access array data (if write command is preceded) or silicon ID codes. 3. With VPP at high voltage, the standby current equals ICC+IPP (standby). 4. Refer to Table 38 for valid Data-In during a write operation. 5. X can be VIL or VIH.
Set-Up Automatic Chip Erase/Erase Commands
The automatic chip erase does not require the device to be entirely pre-programmed prior to executing the Automatic set-up erase command and automatic chip erase command. Upon executing the Automatic chip erase command, the device automatically will program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begins. The erase and verify operations are complete when the data on DQ7 is"1" at which time the device returns to the standby mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Automatic set-up erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. Automatic set-up erase is performed by writing 30H to the command register. To command automatic chip erase, the command 30H must be written again to the command register. The automatic chip erase begins on the rising edge of the WE and terminates when the data on DQ7 is "1 " and the data on DQ6 stops toggling for two consecutive read cycles, at which time the device returns to the standby mode.
Reset Command
A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. Should program-fail or erase-fail happen, two consecutive writes of FFH will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
Write Operation Status Toggle Bit-DQ6
The 89C535/536/538 features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/Erase algorithms are either in progress or completed. While the Automatic Program or Erase algorithm is in progress, successive attempts to read data from the device will result in DQ6 toggling between one and zero. Once the Automatic Program or Erase algorithm is completed, DQ6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the second WE pulse of the two write pulse sequences.
Data Polling-D07
The 89C535/536/538 also features DATA Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation an attempt to read the device will produce the complement data of the data last written to DQ7. Upon completion of the Automatic Program algorithm an attempt to read the device will produce the true data last written to DQ7. The Data Polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequences. While the Automatic Erase algorithm is in operation, DQ7 will read "0" until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read "1". The DATA Polling feature is valid after the rising edge of the second WE pulse of two writes pulse sequences. The DATA Polling feature is active during Automatic Program/Erase algorithms.
Set-Up Automatic Program/Program Commands
The Automatic Set-up Program is a command-only operation that stages the devices for automatic programming. Automatic Set-up Program is performed by writing 40H to the command register. Once the Automatic Set-up Program operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data read on DQ6 stops toggling for two consecutive read cycles and the data on DQ7 and DQ6 are equivalent to data written to these two bits at which time the device returns to the Read mode (no program verify command is required; but data can be read out if OE is active low).
Write Operation
The data to be programmed into Flash should be inverted when programming. In other words to program the value `00', `FF' should be applied to port P0.
1997 Jun 05
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
System Considerations
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is
dependent on the output capacitance loading of the device. At a minimum, a 0.1uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND, and between VPP and GND to minimize transient effects.
SYMBOL CIN COUT
PARAMETER VPPH VPPH
MIN
TYP
MAX 14 16
UNIT PF pF
CONDITION VIN = 0V VOUT = 0V
Command programming/Data programming/Erase Operation
DC CHARACTERISTICS
Tamb = 0C to 70C, VCC = 5V 10%, VPP = 12.0V 5% SYMBOL ILI ILO ISB1 ISB2 ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICC5 (Program Verify) ICC6 (Erase Verify) IPP1 (Read) IPP2 (Program) IPP3 (Erase) IPP4 (Program Verify) IPP5 (Erase Verify) VIL VIH Input Voltage VPP Current Operating VCC Current PARAMETER Input Leakage Current Output Leakage Current Standby VCC Current CONDITION VIN = GND to VCC VOUT = GND to VCC CE = VIH CE = VCC 0.3 V IOUT = 0 mA, f=1 MHz IOUT = 0 mA, F=11MHz In Programming In Erase In Program Verify In erase Verify VPP=12.6 V In Programming In Erase In Program Verify In Erase Verify -0.5 (Note 5) 2.4 1 MIN TYP 10 10 1 100 30 50 50 50 50 50 100 50 50 50 50 0.2VPP - 0.3 VCC+0.3V (Note 6) VOL VOH Output Voltage Low Output Voltage High IOL=2.1mA IOH=400uA 2.4 0.45 V V MAX UNIT A A mA A mA mA mA mA mA mA A mA mA mA mA V V
NOTES: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 14V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP=12V. 4. Do not alter VPP from VIL to 12V or 12V to VIL when CE=VIL 5. VIL min. = -0.5V for pulse width 20ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 7. All currents are in RMS unless otherwise noted. (Sampled, not 100% tested.).
1997 Jun 05
26
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
AC CHARACTERISTICS
Tamb = 0C to 70C, VCC = 5V " 10%, VPP = 12V " 5% SYMBOL VPS OES CWC CEP EPH1 CEPH2 AS AH1 DS DH CESP CES CESC VPH DF DPA AETC AVT PARAMETER VPP setup time OE setup time Command programming cycles WE programming pulse width WE programming pulse width High WE programming pulse width High Address setup time Address hold time for DATA Polling DATA setup time DATA hold time CE setup time before DATA polling/toggle bit CE setup time CE setup time before command write VPP hold time Output disable time (Note 2) DATA polling/toggle bit access time Total erase time in auto chip erase Total programming time in auto verify 15 CONDITION MIN 100 100 150 60 20 100 0 0 50 10 100 0 100 100 35 150 5(TYP) 300 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms
NOTES: 1. CE and OE must be fixed high during VPP transition from 5V to 12V or from 12V to 5V. 2. DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Timing Waveform Automatic Programming
One byte of data is programmed. Verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by an internal control
circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verify starts. Device outputs DATA during programming and DATA after programming on Q7. Q0 to Q5(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
1997 Jun 05
27
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
SETUP AUTO PROGRAM/ PROGRAM COMMAND VCC 5V 12V VPP OV AUTO PROGRAM & DATA POLLING
VPS ADDRESS VALID AS
VPH
A0-A15 WE cwc CE QES OE DS Q7 DH DS DH CEP CEPH1 CEP CESP
AH1 AVT
CES
CESC
DPA DATA
tDF DATA
COMMAND IN
DATA IN
DATA POLLING Q0-Q5 COMMAND IN DATA IN DATA
COMMAD #40H
su00877
Figure 22.
Automatic Programming Timing Waveform 0 during erasure and 1 after erasure on Q7, Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
AUTOMATIC CHIP ERASE All data in the FLASH memory is erased. External erase verification is not required. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs
1997 Jun 05
28
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
RESET
SETUP AUTO CHIP ERASE/ ERASE COMMAND AUTO CHIP ERASE & DATA POLLING VCC 5V
12V VPP OV VPH VPS
A0-A15
WE
CWC CE CEP CEP CESP CES
AETC
QES OE
CEPH1
CESC
DS
DH
DS
DH
DPA
DF
Q7
COMMAND IN
COMMAND IN
DATA POLLING Q0-Q5 COMMAND IN COMMAND IN
su00878
Figure 23.
Automatic Chip Erase Timing Waveform
1997 Jun 05
29
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
VCC 5V 12V VPP 0V VPS
A0-A15
WE
tCWC
CE
QES OE
CEP
CEPH1
CEP
DS
DH
DS
DH
Q0-Q7
COMMAND IN FFH
COMMAND IN FFH
su00879
Figure 24.
Reset Timing Waveform
Toggle Bit, Data Polling
Toggle bit appears in Q6, when program/erase is operating. DATA polling appears in Q7 during programming or erase.
1997 Jun 05
30
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
HIGH WE VPP 12V CE
OE
TOGGLE BIT OE DURING P/E DATA POLLING O7 DURING P O7 DURING P HIGH-Z PROGRAM/ERASE COMPLETE HIGH-Z DATA DATA DATA DATA HIGH-Z DATA
HIGH-Z O0-O5
DATA POLLING DATA
su00880
Figure 25.
Toggle Bit, Data Polling Timing Waveform
1997 Jun 05
31
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1997 June 05
32
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1997 June 05
33
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
NOTES
1997 June 05
34
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers with FLASH program memory
89C535/89C536/89C538
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 June 05 35
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